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FEATURES Excellent Video Specifications (RL = 150 , G = +2) Gain Flatness 0.1 dB to 100 MHz 0.01% Differential Gain Error 0.025 Differential Phase Error Low Power 5.5 mA Max Power Supply Current (55 mW) High Speed and Fast Settling 880 MHz, -3 dB Bandwidth (G = +1) 440 MHz, -3 dB Bandwidth (G = +2) 1200 V/ s Slew Rate 10 ns Settling Time to 0.1% Low Distortion -65 dBc THD, fC = 5 MHz 33 dBm Third Order Intercept, F1 = 10 MHz -66 dB SFDR, f = 5 MHz High Output Drive 70 mA Output Current Drives Up to 4 Back-Terminated Loads (75 Each) While Maintaining Good Differential Gain/Phase Performance (0.05%/0.25 ) APPLICATIONS A-to-D Drivers Video Line Drivers Professional Cameras Video Switchers Special Effects RF Receivers GENERAL DESCRIPTION
800 MHz, 50 mW Current Feedback Amplifier AD8001
FUNCTIONAL BLOCK DIAGRAMS 8-Lead PDIP (N-8), CERDIP (Q-8) and SOIC (R-8)
NC 1 -IN 2 8 7 6 NC VOUT 1 V+ OUT NC -VS 2 +IN 3
4
5-Lead SOT-23-5 (RT-5)
AD8001
5
+VS
+IN 3 V- 4
AD8001
5
-IN
NC = NO CONNECT
transimpedance linearization circuitry. This allows it to drive video loads with excellent differential gain and phase performance on only 50 mW of power. The AD8001 is a current feedback amplifier and features gain flatness of 0.1 dB to 100 MHz while offering differential gain and phase error of 0.01% and 0.025. This makes the AD8001 ideal for professional video electronics such as cameras and video switchers. Additionally, the AD8001's low distortion and fast settling make it ideal for buffer high speed A-to-D converters. The AD8001 offers low power of 5.5 mA max (VS = 5 V) and can run on a single +12 V power supply, while being capable of delivering over 70 mA of load current. These features make this amplifier ideal for portable and battery-powered applications where size and power are critical. The outstanding bandwidth of 800 MHz along with 1200 V/s of slew rate make the AD8001 useful in many general-purpose high speed applications where dual power supplies of up to 6 V and single supplies from 6 V to 12 V are needed. The AD8001 is available in the industrial temperature range of -40C to +85C.
The AD8001 is a low power, high speed amplifier designed to operate on 5 V supplies. The AD8001 features unique
9 6 3 G = +2 RL = 100 VS = 5V RFB = 820
GAIN - dB
0 -3 VS = 5V RFB = 1k
-6 -9 -12 10M
100M FREQUENCY - Hz
1G
Figure 1. Frequency Response of AD8001
Figure 2. Transient Response of AD8001; 2 V Step, G = +2
REV. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD8001-SPECIFICATIONS (@ T = + 25 C, V =
A S
5 V, RL = 100
, unless otherwise noted.)
Min
350 650 350 575 300 575 85 100 120 800 960
Model
DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth, N Package R Package RT Package Bandwidth for 0.1 dB Flatness N Package R Package RT Package Slew Rate Settling Time to 0.1% Rise and Fall Time NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Third Order Intercept 1 dB Gain Compression SFDR DC PERFORMANCE Input Offset Voltage
Conditions
G = +2, < 0.1 dB Peaking, R F = 750 G = +1, < 1 dB Peaking, RF = 1 k G = +2, < 0.1 dB Peaking, R F = 681 G = +1, < 0.1 dB Peaking, R F = 845 G = +2, < 0.1 dB Peaking, R F = 768 G = +1, < 0.1 dB Peaking, RF = 1 k G = +2, R F = 750 G = +2, R F = 681 G = +2, R F = 768 G = +2, VO = 2 V Step G = -1, VO = 2 V Step G = -1, VO = 2 V Step G = +2, VO = 2 V Step, RF = 649 fC = 5 MHz, VO = 2 V p-p G = +2, RL = 100 f = 10 kHz f = 10 kHz, +In -In NTSC, G = +2, R L = 150 NTSC, G = +2, R L = 150 f = 10 MHz f = 10 MHz f = 5 MHz
AD8001A Typ Max
440 880 440 715 380 795 110 125 145 1000 1200 10 1.4 -65 2.0 2.0 18 0.01 0.025 33 14 -66 2.0 2.0 10 5.0 3.0
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz V/s V/s ns ns dBc nV/Hz pA/Hz pA/Hz % Degree dBm dBm dB mV mV V/C A A A A k k M pF V
0.025 0.04
TMIN -TMAX Offset Drift -Input Bias Current TMIN -TMAX +Input Bias Current Open-Loop Transresistance INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Offset Voltage -Input Current +Input Current OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio -Input Current +Input Current
Specifications subject to change without notice.
5.5 9.0 25 35 6.0 10
TMIN -TMAX VO = 2.5 V TMIN -TMAX +Input -Input +Input VCM = 2.5 V VCM = 2.5 V, TMIN -TMAX VCM = 2.5 V, TMIN -TMAX R L = 150 R L = 37.5
250 175
900
10 50 1.5 3.2 50 54 0.3 0.2 3.1 70 110 6.0 5.5
1.0 0.7
dB A/V A/V V mA mA V mA dB dB A/V A/V
2.7 50 85 3.0
TMIN -TMAX +VS = +4 V to +6 V, -VS = -5 V -VS = - 4 V to - 6 V, +VS = +5 V TMIN -TMAX TMIN -TMAX
60 50
5.0 75 56 0.5 0.1
2.5 0.5
-2-
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AD8001
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation @ 25C2 PDIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W 8-Lead CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range N, R . . . . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead PDIP Package: JA = 90C/W 8-Lead SOIC Package: JA = 155C/W 8-Lead CERDIP Package: JA = 110C/W 5-Lead SOT-23-5 Package: JA = 260C/W
The maximum power that can be safely dissipated by the AD8001 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8001 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0 8-LEAD PDIP PACKAGE 1.5 8-LEAD SOIC PACKAGE TJ = +150 C
MAXIMUM POWER DISSIPATION - W
8-LEAD CERDIP PACKAGE
1.0
0.5 5-LEAD SOT-23-5 PACKAGE 0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C
70
80
90
Figure 3. Plot of Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model AD8001AN AD8001AQ AD8001AR AD8001AR-REEL AD8001AR-REEL7 AD8001ART-REEL AD8001ART-REEL7 AD8001ACHIPS 5962-9459301MPA*
*
Temperature Range -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C
Package Description 8-Lead PDIP 8-Lead CERDIP 8-Lead SOIC 13" Tape and REEL 7" Tape and REEL 13" Tape and REEL 7" Tape and REEL Die Form 8-Lead CERDIP
Package Option N-8 Q-8 R-8 R-8 R-8 RT-5 RT-5 Q-8
Branding
HEA HEA
Standard Military Drawing Device.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8001 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD8001-Typical Performance Characteristics
806 +VS 0.001 F 0.1 F 806 VOUT TO TEKTRONIX CSA 404 COMM. SIGNAL ANALYZER
AD8001
VIN HP8133A PULSE GENERATOR TR/TF = 50ps 50 0.1 F 0.001 F -VS RL = 100
400mV
5ns
TPC 1. Test Circuit , Gain = +2
TPC 4. 2 V Step Response, G = +2
909 +VS 0.001 F 0.1 F VOUT TO TEKTRONIX CSA 404 COMM. SIGNAL ANALYZER
AD8001
VIN LeCROY 9210 PULSE GENERATOR TR/TF = 350ps 50 0.1 F 0.001 F -VS RL = 100
TPC 2. 1 V Step Response, G = +2
TPC 5. Test Circuit, Gain = +1
0.5V
5ns
TPC 3. 2 V Step Response, G = +1
TPC 6. 100 mV Step Response, G = +1
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AD8001
9 6 3 G = +2 RL = 100 VS = 5V RFB = 820
1000
800
-3dB BANDWIDTH - MHz
VS = 5V RL = 100 G = +2
GAIN - dB
600
0 -3 VS = 5V RFB = 1k
N PACKAGE
400 R PACKAGE 200
-6 -9 -12 10M
100M FREQUENCY - Hz
1G
0 500
600
700
800
900
1000
VALUE OF FEEDBACK RESISTOR (RF) -
TPC 7. Frequency Response, G = +2
TPC 10. -3 dB Bandwidth vs. RF
0.1 0 -0.1 -0.2 RF = 698
RF = 649
-50 5V SUPPLIES
HARMONIC DISTORTION - dBc
-60
VOUT = 2V p-p RL = 100 G = +2
RF = 750 G = +2 RL = 100 VIN = 50mV
OUTPUT - dB
-0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 1M
-70 SECOND HARMONIC -80 THIRD HARMONIC -90
10M FREQUENCY - Hz
100M
-100 10k
100k
1M FREQUENCY - Hz
10M
100M
TPC 8. 0.1 dB Flatness, R Package (for N Package Add 50 to RF)
TPC 11. Distortion vs. Frequency, RL = 100
DIFF PHASE - Degrees
-50 5V SUPPLIES VOUT = 2V p-p RL = 1k G = +2
0.08 0.06 0.04 0.02 0.00 1 BACK TERMINATED LOAD (150 ) 0.02 G = +2 RF = 806
HARMONIC DISTORTION - dBc
-60
2 BACK TERMINATED LOADS (75 )
-70 SECOND HARMONIC -80
DIFF GAIN - %
-90
THIRD HARMONIC
0.01 0.00 -0.01 -0.02 0
1 AND 2 BACK TERMINATED LOADS (150 AND 75 )
-100
-110 10k
100k
1M FREQUENCY - Hz
10M
100M
IRE
100
TPC 9. Distortion vs. Frequency, RL = 1 k
TPC 12. Differential Gain and Differential Phase
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-5-
AD8001
5 0 900 -5 -10 VIN = -26dBm RF = 909 -15 -20 -25 -30 -35 100M FREQUENCY - Hz 500 600 1000 N PACKAGE
-3dB BANDWIDTH - MHz
GAIN - dB
800 R PACKAGE 700 VIN = 50mV RL = 100 G = +1
600
1G
3G
900 700 800 1000 VALUE OF FEEDBACK RESISTOR (RF) -
1100
TPC 13. Frequency Response, G = +1
TPC 16. -3 dB Bandwidth vs. RF, G = +1
1 0 -1 RF = 649
-40 RL = 100 G = +1 VOUT = 2V p-p
-50
RF = 953
DISTORTION - dBc
-2
-60 SECOND HARMONIC -70
OUTPUT - dB
-3 -4 -5 -6 -7 G = +1 RL = 100 VIN = 50mV
-80
THIRD HARMONIC
-90
-8 -9 2M 10M 100M FREQUENCY - Hz 1G
-100 10k
100k
1M FREQUENCY - Hz
10M
100M
TPC 14. Flatness, R Package, G = +1 (for N Package Add 100 to RF)
TPC 17. Distortion vs. Frequency, RL = 100
-40 G = +1 RL = 1k VOUT = 2V p-p
3 0 -3 -6
OUTPUT - dBV
THIRD HARMONIC
-50 -60 -70
DISTORTION - dBc
-9 -12 -15 -18 -21 RL = 100 G = +1
SECOND HARMONIC -80 -90 -100 -110 10k
-24 -27 1M
100k
1M FREQUENCY - Hz
10M
100M
10M FREQUENCY - Hz
100M
TPC 15. Distortion vs. Frequency, RL = 1 k
TPC 18. Large Signal Frequency Response, G = +1
-6-
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AD8001
45 40 35 30 25 20 GAIN - dB 15 10 5 0 -5 -10 -15 -20 -25 1M 10M 100M FREQUENCY - Hz 1G RL = 100 G = +10 RF = 470 G = +100
INPUT OFFSET VOLTAGE - mV
2.2 2.0 RF = 1000 1.8 1.6 DEVICE NO. 2 1.4 1.2 1.0 0.8 0.6 0.4 -60 DEVICE NO. 3 DEVICE NO. 1
-40
-20 0 20 40 60 JUNCTION TEMPERATURE - C
80
100
TPC 19. Frequency Response, G = +10, G = +100
TPC 22. Input Offset vs. Temperature
3.35 3.25 +VOUT
SUPPLY CURRENT - mA
5.8 5.6 5.4
OUTPUT SWING - Volts
3.15 3.05
RL = 150 VS = 5V
| -VOUT |
2.95 2.85 2.75 2.65 2.55 -60 +VOUT RL = 50 VS = 5V
5.2 5.0 4.8 VS = 5V
| -VOUT |
4.6 4.4 -60
-40
-20 0 20 40 60 JUNCTION TEMPERATURE - C
80
100
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE - C
120
140
TPC 20. Output Swing vs. Temperature
TPC 23. Supply Current vs. Temperature
5 4
125 120
SHORT CIRCUIT CURRENT - mA
INPUT BIAS CURRENT - A
3 -IN 2 1 0 -1 +IN -2 -3 -4 -60
115 110
SOURCE ISC
| SINK ISC |
105 100 95 90 85 -60
-40
-20
0
20
40
60
80
100
120
140
-40
JUNCTION TEMPERATURE - C
-20 0 20 40 60 JUNCTION TEMPERATURE - C
80
100
TPC 21. Input Bias Current vs. Temperature
TPC 24. Short Circuit Current vs. Temperature
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-7-
AD8001
6
1k
5 TRANSRESISTANCE - k VS = 5V RL = 150 VOUT = 2.5V
100
4
10
3 -TZ
ROUT -
1
2
1
+TZ
0.1
G = +2 RF = 909
0 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE - C
120
140
0.01 10k
100k
1M FREQUENCY - Hz
10M
100M
TPC 25. Transresistance vs. Temperature
TPC 28. Output Resistance vs. Frequency
100
100
1 0 RF = 576
NOISE VOLTAGE - nV/Hz
NOISE CURRENT - pA/Hz
INVERTING CURRENT VS =
5V
-1 -2 OUTPUT - dB -3 -4 -5 -6 -7 G = -1 RL = 100 VIN = 50mV RF = 649
10 NONINVERTING CURRENT VS = 5V
10
RF = 750
VOLTAGE NOISE VS = 1 10 100 1k FREQUENCY - Hz
5V 10k 1 100k
-8 -9 1M 10M 100M FREQUENCY - Hz 1G
TPC 26. Noise vs. Frequency
TPC 29. -3 dB Bandwidth vs. Frequency, G = -1
-48 -49 -CMRR -50
-52.5 -55.0 -57.5 -60.0 3V SPAN -PSRR
CMRR - dB
+CMRR -52 -53 2.5V SPAN -54
PSRR - dB
-51
-62.5 -65.0 -67.5 -70.0 -72.5 CURVES ARE FOR WORSTCASE CONDITION WHERE ONE SUPPLY IS VARIED WHILE THE OTHER IS HELD CONSTANT.
-55 -56 -60
+PSRR -75.0
-40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE - C 120 140
-77.5 -60
-40
-20 0 20 40 60 JUNCTION TEMPERATURE - C
80
100
TPC 27. CMRR vs. Temperature
TPC 30. PSRR vs. Temperature
-8-
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AD8001
30 -10 VIN -20 910 150 VOUT PSRR - dB 62 -30 150 0 -10 -20 -30 -40 -50 -50 -60 300k 1M 10M FREQUENCY - Hz 100M 1G 1M 10M 100M FREQUENCY - Hz 1G -PSRR +PSRR RF = 909 G = +2 -PSRR 910 51 20 10 CURVES ARE FOR WORSTCASE CONDITION WHERE ONE SUPPLY IS VARIED WHILE THE OTHER IS HELD CONSTANT. +PSRR
CMRR - dB
-40
TPC 31. CMRR vs. Frequency
TPC 34. PSRR vs. Frequency
1 0 -1 -2 RF = 649 RF = 549
OUTPUT - dB
-3 -4 -5 -6 -7 -8 -9 1M 10M 100M FREQUENCY - Hz 1G G = -2 RL = 100 VIN = 50mVrms
RF = 750
TPC 32. -3 dB Bandwidth vs. Frequency, G = -2
TPC 35. 2 V Step Response, G = -1
100 90 80 70 60
COUNT
100 3 WAFER LOTS COUNT = 895 MEAN = 1.37 STD DEV = 1.13 MIN = -2.45 MAX = +4.69 90 80 CUMULATIVE 70
PERCENT
60 50 FREQ DIST 40 30 20 10 -5 -4 -3 -2 -1 0 1 2 3 INPUT OFFSET VOLTAGE - mV 4 5 0
50 40 30 20 10 0
TPC 33. 100 mV Step Response, G = -1
TPC 36. Input Offset Voltage Distribution
REV. D
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AD8001
THEORY OF OPERATION
A very simple analysis can put the operation of the AD8001, a current feedback amplifier, in familiar terms. Being a current feedback amplifier, the AD8001's open-loop behavior is expressed as transimpedance, VO/I-IN, or TZ. The open-loop transimpedance behaves just as the open-loop voltage gain of a voltage feedback amplifier, that is, it has a large dc value and decreases at roughly 6 dB/octave in frequency. Since the RIN is proportional to 1/gM, the equivalent voltage gain is just TZ x gM, where the gM in question is the transconductance of the input stage. This results in a low open-loop input impedance at the inverting input, a now familiar result. Using this amplifier as a follower with gain, Figure 4, basic analysis yields the following result. TZ (S ) VO =Gx VIN TZ (S ) + G x RIN + R1 G = 1+ R1 R2 RIN = 1 / g M 50
Considering that additional poles contribute excess phase at high frequencies, there is a minimum feedback resistance below which peaking or oscillation may result. This fact is used to determine the optimum feedback resistance, R F. In practice, parasitic capacitance at Pin 2 will also add phase in the feedback loop, so picking an optimum value for R F can be difficult. Figure 6 illustrates this problem. Here the fine scale (0.1 dB/ div) flatness is plotted versus feedback resistance. These plots were taken using an evaluation card which is available to customers so that these results may readily be duplicated. Achieving and maintaining gain flatness of better than 0.1 dB at frequencies above 10 MHz requires careful consideration of several issues.
0.1 0 RF = 698 -0.1 -0.2
OUTPUT - dB
RF = 649
G = +2 -0.3 -0.4 -0.5 -0.6
RF = 750
R1 R2 RIN
VOUT
-0.7 -0.8
VIN
-0.9 1M
10M FREQUENCY - Hz
100M
Figure 4. Follower with Gain
Figure 6. 0.1 dB Flatness vs. Frequency
Choice of Feedback and Gain Resistors
Recognizing that G x RIN << R1 for low gains, it can be seen to the first order that bandwidth for this amplifier is independent of gain (G). This simple analysis in conjunction with Figure 5 can, in fact, predict the behavior of the AD8001 over a wide range of conditions.
1M
100k
Because of the above-mentioned relationship between the bandwidth and feedback resistor, the fine scale gain flatness will, to some extent, vary with feedback resistance. It, therefore, is recommended that once optimum resistor values have been determined, 1% tolerance values should be used if it is desired to maintain flatness over a wide range of production lots. In addition, resistors of different construction have different associated parasitic capacitance and inductance. Surface-mount resistors were used for the bulk of the characterization for this data sheet. It is not recommended that leaded components be used with the AD8001.
10k
TZ -
1k
100
10 100k
1M
10M FREQUENCY - Hz
100M
1G
Figure 5. Transimpedance vs. Frequency
-10-
REV. D
AD8001
Printed Circuit Board Layout Considerations Driving Capacitive Loads
As to be expected for a wideband amplifier, PC board parasitics can affect the overall closed-loop performance. Of concern are stray capacitances at the output and the inverting input nodes. If a ground plane is to be used on the same side of the board as the signal traces, a space (5 mm min) should be left around the signal lines to minimize coupling. Additionally, signal lines connecting the feedback and gain resistors should be short enough so that their associated inductance does not cause high frequency gain errors. Line lengths on the order of less than 5 mm are recommended. If long runs of coaxial cable are being driven, dispersion and loss must be considered.
Power Supply Bypassing
The AD8001 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best frequency response is obtained by the addition of a small series resistance, as shown in Figure 8. The accompanying graph shows the optimum value for RSERIES versus capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL.
909
Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier's response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 F) will be required to provide the best settling time and lowest distortion. A parallel combination of 4.7 F and 0.1 F is recommended. Some brands of electrolytic capacitors will require a small series damping resistor 4.7 for optimum results.
DC Errors and Noise
RSERIES IN RL 500 CL
Figure 8. Driving Capacitive Loads
40 G = +1 30
There are three major noise and offset terms to consider in a current feedback amplifier. For offset errors, refer to the equation below. For noise error the terms are root-sum-squared to give a net output error. In the circuit in Figure 7 they are input offset (VIO), which appears at the output multiplied by the noise gain of the circuit (1 + RF/RI), noninverting input current (IBN x RN) also multiplied by the noise gain, and the inverting input current, which when divided between RF and RI and subsequently multiplied by the noise gain always appears at the output as IBN x RF. The input voltage noise of the AD8001 is a low 2 nV/ Hz. At low gains though the inverting input current noise times RF is the dominant noise source. Careful layout and device matching contribute to better offset and drift specifications for the AD8001 compared to many other current feedback amplifiers. The typical performance curves in conjunction with the following equations can be used to predict the performance of the AD8001 in any application.
R R VOUT = VIO x 1 + F I BN x RN x 1 + F I BI x RF RI RI
RF RI IBI
RSERIES -
20
10
0
0
5
10 CL - pF
15
20
25
Figure 9. Recommended RSERIES vs. Capacitive Load
RN
IBN
VOUT
Figure 7. Output Offset Voltage
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AD8001
Communications Operation as a Video Line Driver
Distortion is a key specification in communications applications. Intermodulation distortion (IMD) is a measure of the ability of an amplifier to pass complex signals without the generation of spurious harmonics. The third order products are usually the most problematic since several of them fall near the fundamentals and do not lend themselves to filtering. Theory predicts that the third order harmonic distortion components increase in power at three times the rate of the fundamental tones. The specification of third order intercept as the virtual point where fundamental and harmonic power are equal is one standard measure of distortion performance. Op amps used in closed-loop applications do not always obey this simple theory. At a gain of +2, the AD8001 has performance summarized in Figure 10. Here the worst third order products are plotted versus input power. The third order intercept of the AD8001 is +33 dBm at 10 MHz.
-45 -50 G = +2 F1 = 10MHz F2 = 12MHz -55 -60 -65 -70 -75 -80 -8 -7 2F1 - F2 2F2 - F1
The AD8001 has been designed to offer outstanding performance as a video line driver. The important specifications of differential gain (0.01%) and differential phase (0.025) meet the most exacting HDTV demands for driving one video load. The AD8001 also drives up to two back terminated loads as shown in Figure 11, with equally impressive performance (0.01%, 0.07). Another important consideration is isolation between loads in a multiple load application. The AD8001 has more than 40 dB of isolation at 5 MHz when driving two 75 back terminated loads.
909 909 +VS 75 75 CABLE VOUT NO. 1 75
0.001 F + 0.1 F 75 CABLE
75 CABLE VIN 75
AD8001
0.1 F
75
VOUT NO. 2 75
THIRD ORDER IMD - dBc
0.001 F -VS
Figure 11. Video Line Driver
-6
-5
-4
-3 -2 -1 0 1 INPUT POWER - dBm
2
3
4
5
6
Figure 10. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz
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AD8001
Driving A-to-D Converters
The AD8001 is well suited for driving high speed analog-todigital converters such as the AD9058. The AD9058 is a dual 8-bit 50 MSPS ADC. In the circuit below, the AD8001 is shown driving the inputs of the AD9058, which are configured for 0 V to 2 V ranges. Bipolar input signals are buffered, amplified (-2x), and offset (by +1.0 V) into the proper input range of the
ADC. Using the AD9058's internal +2 V reference connected to both ADCs as shown in Figure 12 reduces the number of external components required to create a complete data acquisition system. The 20 resistors in series with ADC inputs are used to help the AD8001s drive the 10 pF ADC input capacitance. The AD8001 only adds 100 mW to the power consumption while not limiting the performance of the circuit.
1k ENCODE 10 ENCODE A 649 ANALOG IN A 0.5V 324 20 8 38 6 -VREF A -VREF B 36 ENCODE B +VS 5, 9, 22, 24, 37, 41 0.1 F RZ1 18 17 15 14 +VREF A +VREF B D7A (MSB) 649 D0B (LSB) ANALOG IN B 0.5V 324 20 13 12 11 28 29 31 AIN B 32 33 1 0.1 F COMP D7B (MSB) -VS RZ1, RZ2 = 2,000 SIP (8-PKG) 4,19, 21 25, 27, 42 34 35 7, 20, 26, 39 0.1 F -5V 1N4001 CLOCK 30 RZ2 16 -2V 2 +5V 50 74ACT04 10pF
AD9058
(J-LEAD)
AD8001
1.3k
AIN A
D0A (LSB)
AD707
0.1 F 20k 1.3k
+VINT
74ACT 273 74ACT 273
8
20k 0.1 F
3 43
AD8001
40
8
Figure 12. AD8001 Driving a Dual A-to-D Converter
REV. D
-13-
AD8001
Layout Considerations
The specified high speed performance of the AD8001 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing (see Figure 13). One end should be connected to the ground plane and the other within 1/8 inch of each power pin. An additional large
RF +VS RG IN RT RS -VS -VS RO OUT C2 0.1 F +VS C1 0.1 F
(4.7 F-10 F) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large-signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about 1 inch). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end.
RF +VS C3 10 F C4 10 F IN RT -VS RG RO OUT
Inverting Configuration
Supply Bypassing
Noninverting Configuration
Figure 13. Inverting and Noninverting Configurations for Evaluation Boards
Table I. Recommended Component Values
AD8001AN (PDIP) Gain Component RF () RG () RO (Nominal) () RS () RT (Nominal) () Small Signal BW (MHz) 0.1 dB Flatness (MHz) -1 649 649 49.9 0 54.9 340 105 +1 1050 49.9 49.9 880 70 +2 750 750 49.9 49.9 460 105 +10 470 51 49.9 49.9 260 +100 1000 10 49.9 49.9 20 -1 604 604 49.9 0 54.9 370 130 AD8001AR (SOIC) Gain +1 953 49.9 49.9 710 100 +2 681 681 49.9 49.9 440 120 +10 470 51 49.9 49.9 260 +100 1000 10 49.9 49.9 20 -1 845 845 49.9 0 54.9 240 110 AD8001ART (SOT-23-5) Gain +1 +2 +10 470 51 49.9 49.9 260 +100 1000 10 49.9 49.9 20
1000 768 768 49.9 49.9 49.9 795 300 49.9 380 145
-14-
REV. D
AD8001
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP] (N-8)
Dimensions shown in inches and (millimeters)
0.375 (9.53) 0.365 (9.27) 0.355 (9.02)
8 5
8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8)
Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN
8
0.055 (1.40) MAX
5
1
4
0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) MIN SEATING PLANE 0.060 (1.52) 0.050 (1.27) 0.045 (1.14)
PIN 1
1 4
0.310 (7.87) 0.220 (5.59)
0.100 (2.54) BSC 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.100 (2.54) BSC
0.150 (3.81) 0.135 (3.43) 0.120 (3.05)
0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15 0
0.320 (8.13) 0.290 (7.37)
0.015 (0.38) 0.010 (0.25) 0.008 (0.20)
0.015 (0.38) 0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Standard Small Outline Package [SOIC] (R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968) 4.80 (0.1890)
8 5 4
5-Lead Small Outline Transistor Package [SOT-23] (RT-5)
Dimensions shown in millimeters
2.90 BSC
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2440) 5.80 (0.2284)
5
4
1.60 BSC
1 2 3
2.80 BSC
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.17 (0.0067)
0.50 (0.0196) 0.25 (0.0099)
45 1.30 1.15 0.90
PIN 1 0.95 BSC 1.90 BSC
0.51 (0.0201) 0.31 (0.0122)
1.27 (0.0500) 0.40 (0.0157)
1.45 MAX
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.22 0.08 10 5 0 0.60 0.45 0.30
0.15 MAX
0.50 0.30
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AA
REV. D
-15-
AD8001
Revision History
7/03--Data Sheet changed from REV. C to REV. D
Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
-16-
REV. D
C01043-0-7/03(D)
Location
Page

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